NVIDIA announced the Vera CPU at the June 1 COMPUTEX 2026 keynote. The name has appeared in coverage of the Vera Rubin NVL72 rack — where 36 Vera CPUs pair with 72 Rubin GPUs in a liquid-cooled chassis — but the CPU is also a standalone server product shipping H2 2026 from 18+ OEM partners and a handful of cloud providers.
This is worth understanding separately from the GPU rack story. Vera CPU is NVIDIA’s claim that the non-GPU parts of the AI data center — orchestration, agent runtime, reinforcement learning loops, data preprocessing, graph traversal — are under-served by x86, and that a purpose-built processor can close that gap. The company’s benchmark: 1.8x faster task completion than leading x86 CPUs on agentic workloads.
Whether that claim holds in production is something H2 2026 deployments will prove or disprove. Here is what builders need to know now.
What NVIDIA Vera CPU Actually Is
Vera is a server CPU, not a laptop chip or a GPU. It ships in rack server form factors from standard OEM partners — the same companies (Dell, HPE, Supermicro) that sell x86 servers. The target workloads are the CPU-bound jobs that run alongside GPU-accelerated inference in an AI factory: agent orchestration, reinforcement learning loops, memory-intensive data processing, and graph analytics.
NVIDIA has called it “the first server CPU purpose-built for the age of agentic AI.” Whether that framing is accurate depends on whether the Olympus core architecture actually delivers meaningfully different performance characteristics for those workloads than a modern x86 chip — which the technical data suggests it does, for specific access patterns.
Vera is the successor to NVIDIA Grace (used in GH200 Grace Hopper systems). Grace was a capable Arm-based server chip, but was designed primarily as a CPU pairing for GPU-intensive inference. Vera is intended to stand alone as a server processor for agentic workloads — and also to pair with Rubin GPUs in the NVL72 rack.
The Olympus Core Architecture
The central engineering bet in Vera is the Olympus core — a custom NVIDIA-designed Arm v9.2 ISA core built from scratch rather than licensed from Cortex.
Core count and threading:
- 88 Olympus cores per processor
- 176 hardware threads via Spatial Multithreading
Spatial Multithreading is meaningfully different from conventional Simultaneous Multithreading (SMT). Traditional SMT time-slices execution resources between threads. Spatial Multithreading physically partitions the core’s resources at runtime to present 176 hardware threads simultaneously. For workloads with high branch divergence — agent decision trees, policy evaluation, irregular memory access — this design reduces thread-switching overhead.
Per-core improvements over NVIDIA Grace:
- 50% higher IPC (wider front end, advanced branch prediction, deeper out-of-order scheduling)
- 2x L2 cache (2 MB per core)
- Larger unified L3 cache (164 MB total)
- Specialized memory prefetching tuned for agentic code patterns
FP8 support: Olympus cores support FP8 precision natively. Most CPU workloads in AI inference run in FP32 or INT8; FP8 enables compressed model weights and activations to pass between CPU and GPU without upconversion. This matters for bandwidth efficiency in hybrid CPU-GPU agent pipelines.
Memory Architecture: 1.2 TB/s and Graph Traversal
The memory subsystem is where Vera departs most sharply from x86 server chips.
Bandwidth:
- 1.2 TB/s total memory bandwidth
- LPDDR5X via 8 SOCAMM modules (detachable, field-replaceable)
- 3x bandwidth per core compared to leading x86 CPUs with DDR5
The SOCAMM format is significant for enterprise operators: memory modules are field-replaceable without replacing the processor. DDR5-based x86 server platforms do not offer equivalent per-core bandwidth at these levels.
Graph prefetcher:
Vera includes a graph prefetcher specifically designed for indirect memory access patterns — the kind generated by graph analytics and agent memory traversal (following chains of pointers through knowledge graphs, document stores, or multi-hop retrieval pipelines). NVIDIA claims more than 3x performance on graph traversal workloads compared to x86.
This is the most interesting benchmark for builders running RAG pipelines or knowledge graph-backed agents. Graph traversal is typically CPU-bound after the embedding step, and it is notoriously unfriendly to standard prefetchers because the next memory address to access is determined by the current memory read (pointer chasing). A hardware prefetcher designed for this pattern rather than linear sequential reads is a genuine architectural differentiation — if the 3x claim holds across realistic workloads rather than synthetic benchmarks.
GPU Connectivity: NVLink-C2C
In configurations that pair Vera CPU with Rubin GPUs (as in the NVL72 rack), the interconnect is second-generation NVLink-C2C at 1.8 TB/s coherent bandwidth between CPU and GPU.
This is not PCIe. PCIe Gen 5 (current generation x86 GPU servers) tops out around 128 GB/s per x16 slot. PCIe Gen 6 (supported on Vera, for PCI-attached peripherals) reaches 256 GB/s per x16. NVLink-C2C at 1.8 TB/s is approximately 7x PCIe Gen 6 bandwidth, and it is coherent — the CPU and GPU share a unified memory address space, with cache coherence maintained in hardware.
For agent workloads where the CPU handles orchestration and the GPU handles inference, coherent shared memory eliminates explicit copy operations between CPU and GPU memory buffers. In long-horizon agent pipelines where the context window contents move between compute stages frequently, this matters for latency.
In standalone Vera CPU server configurations (no Rubin GPU in the same chassis), the CPU connects to GPU accelerators via PCIe Gen 6 plus CXL 3.1 — which still offers more bandwidth than current-generation x86 GPU server interconnects.
Performance Claims vs. X86
NVIDIA’s official published benchmarks:
| Workload | Vera CPU vs. x86 |
|---|---|
| Agentic AI task completion | 1.8x faster |
| AI-focused workloads (general) | Up to 80% faster |
| Graph traversal | More than 3x faster |
| Instructions per clock vs. Grace (NVIDIA’s prior CPU) | 50% higher |
| Memory bandwidth per core vs. x86 DDR5 | 3x higher |
These are vendor-published figures. Independent benchmarks (Phoronix ran early Vera benchmarks and confirmed Olympus core performance above Grace) support the IPC claims. Production workload data from cloud deployments — which will arrive in H2 2026 — will be the real test. The graph traversal claim in particular warrants verification on actual RAG workloads before infrastructure decisions are made on the basis of it.
How Vera CPU Fits the COMPUTEX Hardware Stack
COMPUTEX 2026 completed NVIDIA’s four-tier compute stack for the agentic AI era:
| Tier | Product | Target | Availability |
|---|---|---|---|
| Laptop/Edge | RTX Spark | Local inference, Windows agentic OS | Fall 2026 |
| Deskside | DGX Station for Windows | Enterprise on-prem (GB300 Grace Blackwell) | Q4 2026 |
| Server CPU | Vera CPU | AI factory orchestration, RL, agent runtime | H2 2026 |
| GPU Rack | Vera Rubin NVL72 | Frontier inference, large-scale training | H2 2026 |
Vera CPU occupies a distinct slot: it is the CPU tier of the AI factory, not the GPU tier. In a datacenter running NVL72 racks, Vera CPU servers handle the work that cannot or should not run on GPU: orchestration logic, scheduling, RL policy updates, retrieval preprocessing, logging, and the control plane of multi-agent systems.
The alternative — running that orchestration work on x86 servers that sit alongside GPU racks — creates a bandwidth bottleneck whenever context windows or retrieved chunks need to move between the orchestration layer and the inference layer. Vera CPU with NVLink-C2C eliminates that bottleneck in the NVL72 configuration; Vera CPU standalone servers reduce it via PCIe Gen 6 + CXL 3.1.
DSX: The Software Layer
NVIDIA announced DSX (Data Center Software eXperience) alongside the Vera CPU. DSX is NVIDIA’s unified framework for AI factory management, comprising:
- DSX MaxLPS: Power and cooling optimization delivering up to 40% more GPU capacity within the same power envelope
- DSX OS: Open-source software stack for managing agentic AI data centers; manages GPU scheduling, NVLink fabric, and agent job routing
DSX OS is the software surface that Vera CPU systems run in AI factory configurations. It is open source and extensible — builders at cloud providers or running their own AI factories can customize scheduling and routing logic.
Who Is Deploying Vera CPU
OEM server partners (H2 2026 availability):
Aivres, ASRock Rack, ASUS, Compal, Dell, Foxconn, GIGABYTE, HPE, Hyve Solutions, Inventec, Lenovo, MiTAC Computing, MSI, Pegatron, Quanta Cloud Technology, Supermicro, Wistron, Wiwynn.
HPE announced the ProLiant Compute DL394 Gen12 specifically — a 2U Vera CPU server targeting RL, agentic inference, and data processing workloads. ASRock Rack announced the 2UXGM-VERA2.
Cloud providers committing to Vera CPU deployments:
Alibaba Cloud, ByteDance, Cloudflare, CoreWeave, Crusoe, Lambda, Nebius, Nscale, Oracle Cloud Infrastructure, Together.AI, Vultr.
The cloud provider list is the one that matters most for the majority of builders. When Lambda, CoreWeave, and Together.AI deploy Vera CPU clusters, the per-token costs on their inference APIs should reflect the efficiency gains — without builders needing to procure or manage Vera CPU hardware.
When Does Vera CPU Matter for Builders
You are a cloud API builder: It mostly matters indirectly. When your inference providers (Lambda, CoreWeave, Together, Oracle) deploy Vera CPU clusters to handle the CPU-side of agentic workloads, the efficiency gains should show up in pricing and latency — especially for graph-backed retrieval and multi-agent orchestration patterns. Watch H2 2026 pricing announcements from those providers.
You are building on-prem AI infrastructure at scale: Vera CPU is a genuine consideration for the non-GPU servers in your stack. The 3x graph traversal performance and 1.2 TB/s memory bandwidth are meaningful if your agents run multi-hop retrieval pipelines. The field-replaceable SOCAMM memory modules reduce maintenance overhead. The question is whether the premium over x86 (no published pricing, but ARM data center CPUs typically carry a premium) is justified by actual workload performance — which you should benchmark on your specific patterns before committing.
You are building RAG or knowledge graph workloads: The graph prefetcher claim is the most interesting architectural differentiation for this use case. More than 3x on graph traversal on realistic workloads — not just synthetic benchmarks — would be a significant input to infrastructure decisions for graph-backed retrieval at scale.
You are a small team using managed APIs: Vera CPU is several layers removed from your decisions. Your infrastructure layer handles it; you see the results in API performance over time.
What Is Not Resolved Yet
- Pricing: No published pricing for Vera CPU standalone servers. OEM pricing varies. Cost-per-workload comparison against x86 alternatives requires production data.
- Independent benchmarks: Phoronix confirmed Olympus IPC improvements over Grace. Production workload benchmarks across RL, agent orchestration, and realistic RAG pipelines are not yet published.
- Cloud pricing impact: When Vera CPU deployments go live at Lambda, CoreWeave, and others, whether per-token or per-second pricing reflects efficiency gains depends on each provider’s pricing strategy.
- Software maturity: DSX OS is open source but new. Operational stability and ecosystem tooling will take time to develop.
The One-Line Summary
NVIDIA Vera CPU is the server processor the company has been missing to complete its end-to-end AI factory story: a purpose-built CPU that handles agent orchestration, RL loops, and graph traversal faster than x86, with memory bandwidth and NVLink-C2C coherency that removes the bottleneck between the orchestration and inference layers. It ships H2 2026 — watch Lambda, CoreWeave, Together.AI, and Oracle Cloud Infrastructure for the first deployments that will tell builders whether the benchmark claims hold on real workloads.