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Wafer.ai published a production benchmark this week that belongs in every builder’s infrastructure reading list. They ran GLM-5.2 on AMD MI355X hardware, measured it against NVIDIA Blackwell (B200), and published the full methodology. The result: 2,626 tokens per second per node at saturation, 80% of B200 throughput, at roughly 37% of B200 cost per GPU.

That math changes how you think about inference infrastructure.

What Was Measured

Wafer.ai used GLM-5.2 — Zhipu’s 1M-context MoE model — as the test subject. The production workload:

  • Aggregate benchmark: 20,000-token input / 1,000-token output, 60% cache hit rate
  • Single-stream benchmark: 10,000-token input / 1,500-token output (Artificial Analysis standard)
  • Hardware: AMD MI355X cluster

Results at saturation:

Metric Value
Aggregate throughput 2,626 tok/s/node at 2.4 RPS
Single-stream throughput 213 tok/s
TTFT (p50, at saturation) 0.81s
TTFT (p95, at saturation) 2.22s

For comparison: B200 on the same workload reached ~3,192 tok/s/node at 3.0 RPS. MI355X delivers 82% of that throughput.

The Cost Math

The GPU pricing comparison Wafer.ai uses: AMD MI355X is 2.75x cheaper per GPU than Blackwell.

If you’re getting 82% of B200 throughput at 36% of B200 GPU cost, your cost-per-token on MI355X is roughly 44% of what you’d pay on B200. That’s not a marginal edge — it’s the difference between a workload being economically viable at scale and not.

The crossover point depends on your throughput requirements. If you need B200-class throughput (and the 18% difference matters for latency SLAs), Blackwell is still the answer. If your workload can absorb slightly lower throughput for meaningfully lower cost, MI355X is now a serious option.

The Technical Stack

Wafer.ai didn’t just swap hardware and hope for the best. Getting MI355X to 82% of B200 throughput required specific tooling choices:

Inference framework: sglang over vLLM

Wafer tested both. sglang won for this workload. They don’t publish the delta, but the recommendation is explicit: for MoE architectures like GLM-5.2 at long-context, sglang’s scheduling produces better GPU utilization on AMD.

Quantization: MXFP4 via AMD Quark, not FP8

This is a meaningful detail. AMD Quark (AMD’s quantization toolkit) implements MXFP4 quantization that Wafer characterizes as lossless versus FP8. The standard CUDA path for cost-sensitive inference usually reaches for FP8; on AMD at this generation, MXFP4 with Quark delivers comparable or better output quality with stronger throughput characteristics.

Parallelism: TP4×DP2

Tensor Parallelism 4 × Data Parallelism 2 was the winning configuration for this workload size. The specific split matters for memory bandwidth utilization on HBM3E; the takeaway for builders is that AMD doesn’t automatically get the same default configurations that CUDA inference frameworks have optimized over years of GPU-specific tuning.

Speculative decoding enabled

Wafer enabled speculative decoding, contributing meaningfully to single-stream throughput. This is not AMD-specific — it’s available on NVIDIA too — but it’s worth noting that the full optimization bundle was applied, making the results representative of what a tuned production deployment looks like.

The CUDA Moat Thesis

Wafer’s conclusion is blunt: “SOTA on AMD is becoming more a matter of support, not software. The CUDA moat is eroding in real time."

The implication: the historical reason to avoid AMD for LLM inference was ecosystem friction. CUDA-native kernels, CUDA-native frameworks, and years of NVIDIA-specific optimization work meant that AMD hardware — even hardware with competitive specs — underperformed because the software layer hadn’t caught up. That’s been the story since the transformer revolution.

What’s changing is that ROCm has matured, sglang and vLLM both have AMD backends that see active development, and tools like AMD Quark are closing the quantization gap. The raw hardware specs of MI355X (288GB HBM3E, competitive memory bandwidth) were always potentially competitive with Blackwell; the friction was running production inference efficiently on it.

That friction is not gone — Wafer’s result required careful framework selection, quantization tooling, and parallelism configuration that you don’t need to think about as carefully on CUDA. But the gap between “NVIDIA just works better” and “AMD is viable with engineering investment” is closing.

When AMD MI355X Makes Sense for Your Stack

Good fit:

  • Long-context MoE workloads (the benchmark profile)
  • Cost-sensitive batch inference where 18% throughput delta is acceptable
  • Teams with ROCm / sglang experience or willingness to build it
  • Workloads where you’re provisioning months ahead (AMD availability is improving but still requires planning)

Poor fit:

  • Latency-sensitive real-time inference where p95 TTFT matters
  • Workloads where you need day-0 support for new model architectures (CUDA ecosystem ships first)
  • Teams without GPU optimization engineering capacity — you’ll burn the cost savings debugging ROCm

The neutral signal:

The AMD cloud buildout is accelerating. TensorWave’s $350M Series B (June 2026) is explicitly AMD-only, with MI355X capacity expanding. Lambda Labs and other GPU cloud providers are adding AMD options. Supply is no longer the constraint it was in 2024-2025.

What This Means for the Inference Market

Two shifts are underway simultaneously:

AMD viability compresses margins. If 37% of B200 GPU cost delivers 82% of throughput, NVIDIA-based inference providers face pressure on pricing. Customers who can absorb slightly lower throughput (batch jobs, async agents, document processing) have a cost-competitive alternative. NVIDIA’s margin structure in inference compute depends partly on having no credible alternative at competitive capability; MI355X erodes that.

The GLM-5.2 angle is not incidental. Wafer chose a Chinese open-weights model for this benchmark — not Llama, not Mistral. GLM-5.2 is a 1M-context MoE with open weights and an Apache-2.0 license. Its architecture (MoE, long-context) represents a class of model that has been harder to run efficiently outside NVIDIA. Getting it to 82% of B200 throughput on AMD is meaningful validation that the MI355X story isn’t limited to simple dense models.

Builder Action Items

  1. Benchmark your actual workload, not this one. Wafer’s 20k/1k with 60% cache hit rate may not match your traffic. Run your own workload profile before committing capacity.

  2. Evaluate sglang on AMD before vLLM. For long-context MoE, sglang has better AMD support in mid-2026. This will change, but for current projects, start there.

  3. AMD Quark for quantization. If you’re going MXFP4 on AMD, Quark is the current recommendation over trying to adapt FP8 pipelines from CUDA.

  4. Model the cost math with throughput SLAs. The 82% / 37% cost ratio is the starting point, not the answer. Your SLA on TTFT p95 determines whether the gap is acceptable.

  5. Watch TensorWave and Lambda for MI355X availability. Spot pricing and reserved capacity options are emerging. The supply constraint that made AMD purely theoretical in 2024 has materially improved.

The wafer.ai post is here: GLM-5.2 on AMD MI355X. For the TensorWave funding context that explains why MI355X supply is increasing, see our June 2026 piece on their $350M Series B.